1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a row redundancy repair scheme of a semiconductor memory device.
2. Description of the Related Art
Recent advances in semiconductor fabrication increase the degree of integration of semiconductors, particularly semiconductor memory devices. FIG. 1 illustrates a schematic layout of a conventional highly integrated semiconductor memory device. This semiconductor memory device includes a plurality of memory cell arrays ARRAY and peripheral circuit blocks PERI. Also, column decoder blocks CDEC and row decoder/repair redundancy blocks RDC & RED are installed around each of the memory cell arrays ARRAY.
FIG. 2 is a detailed diagram illustrating the connection of a row decoder/repair redundancy block RDEC & RED to the peripheral circuit block PERI shown in the layout of FIG. 1. Referring to FIG. 2, the row decoder/repair redundancy block RDEC & RED includes a plurality of segment blocks 21, 23, 27 and 29. FIG. 2 illustrates a row decoder/repair redundancy block RDEC & RED that includes four segment blocks. However, the number of segment blocks included in a row decoder/repair redundancy block RDEC & RED is not limited. Each of the segment blocks 21 through 29 includes m repair redundancy blocks BLK0 through BLK15, and each of the m repair redundancy blocks BLK0 through BLK15 includes n repair redundant word lines SWL (m and n are natural numbers). Specifically, FIG. 2 illustrates a case where m is 16 and n is 2.
Referring to FIG. 2, 32 repair signal transmission lines for each of the segment blocks 21 through 29 are connected to a control circuit 20 in the peripheral circuit block PERI. That is, a total of 128 repair signal transmission lines REDREP<0:127> of the four segment blocks 21 through 29 are connected to the control circuit 20. The control circuit 20 generates repair signals to select repair redundant word lines SWL and transmits them to the repair redundancy blocks BLK0 through BLK15 via the repair signal transmission lines REDREP<0:127>.
As described above, this conventional semiconductor memory device requires 128 repair signal transmission lines REDREP<0:127> for one row decoder/repair redundancy block RDEC & RED. As a result, the chip length of the conventional semiconductor memory device is greater in the Y-axis direction of the layout of FIG. 1 than in the X-axis direction. This makes the conventional semiconductor memory device difficult to package.